AnsweredAssumed Answered

ADRF6720, PLL lock.

Question asked by Alexander_1989 on May 30, 2016
Latest reply on Jul 19, 2016 by gyaliniz


We are working with chip ADRF6720 and we want to turn PLL lock. If the lock detect signal is available as one of the selectable outputs through the MUXOUT pin 1, with a logic high signifying that the loop is locked, but we can’t see it. When we changed data in 0x02, 0x03 and 0x04 registers, we didn’t see any changes of output frequency on pin 24.

Could you write example of correct sequence for PLL locked .


Best regard.