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ADF4155: output stage

Question asked by luca.banchi on May 30, 2016
Latest reply on Jun 10, 2016 by Brigid.Duggan

Dear support.

 

Regarding the ADF4155, I want to use this chip in my new design in order to realize an integer-N PLL with an external VCO. The VCO works in the range 4200MHz to 4360MHz, with an output level of about +4dBm.

In order to implement the Mute Till Lock function, I want to mute the VCO output frequency by using the ADF4155 Output Stage (PDB_RF), this will simplify a lot my design. In this process, I will set the output divider to 1, and I will externally control the PDB_RF pin.

On the ADF4155 datasheet the reported RF_OUT Maximum Output Frequency is 4000MHz, do you have any experimental data regarding the  RF_OUT performance above 4000MHz (4200-4360 MHz)?

 

Moreover, on the ADF4155 datasheet I read: "For best spur performance, it is recommended to use the VCO output and disable the RF output (Bit DB6, Register 6) stage".

Could you please comment this in case of integer-N PLL?

Is the output stage impact also on the PLL phase noise performance?

 

Thank you

Luca

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