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CLK_OUT of AD9361

Question asked by Usher on May 26, 2016
Latest reply on Nov 25, 2016 by MilanZ

Hello ADI folks,

 

     Couple problems had encountered when I used CLK_OUT of AD9361 with  AD-FMCOMMS2-EBZ. I have following questions need your help.

 

1. CLK_OUT pin belongs to general purpose output or digital interface? This decides logical level high and logic level low because VDD_GPO = 3.3 V but VDD_INTERFACE = 1.8 V.

 

2. What kind the waveform should be present on CLK_OUT pin? Sine wave, square wave  or triangle wave?

 

3. Per Q2, what's the lowest voltage(Vmin) and highest voltage(Vmax) of the CLK_OUT swing? Should there have DC offset to make the CLK_OUT swing is always great than 0V?

 

4. What we observed is that CLK_OUT swing was reduced when CLK_OUT frequency went up. For example, the Vpp is around 2V (-1V to +1V) when frequency set to be ADC_CLK/64 but Vpp is degraded to 1V (-0.5V to +0.5V) when it's frequency to be ADC_CLK/16. Is that normal? 

 

Final, thank you guys for help in advance.

 

Usher

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