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AD9789 Channelizer Mode problem ...

Question asked by kappasm on Jul 21, 2011
Latest reply on Mar 22, 2013 by


I'm testing the possibility of AD9789 to work with multi-channel output.


To test it I built a DDS with FPGA and send to DAC the data in 16-bit wide
Complex Mode on 32-bit bus. I have connected all bus, clock and power.
After powerd on I have follow Page 62 to init DAC without any problem.


The DAC is so configured:


Fdac = 2048 MHz


Foutput RF central = 474 MHz


Interpolatro factor is 16 (2^4, Filter 0 = bypass)


DCO output fequency = 64 MHz (Fdacclk / 32)


FS buad rate is 9.14285 MHz (P/Q = 7/8)


Configuration meets the constraints :


Fdac = I * P/Q * 16 * Fbaud


I activated a "Channelizer Mode" and only Channel 0 is on.


This is all Register :


    0x06, 0xC1      // Set up digital datapath
    0x07, 0x00      //
    0x08, 0x0D      //
    0x09, 0x20      //
    0x0A, 0xFF      //
    0x0B, 0xFF      //
    0x0C, 0xB3      //
    0x0D, 0x00      //
    0x0E, 0x00      //
    0x0F, 0x00      //
    0x10, 0x00      //
    0x11, 0x00      //
    0x12, 0x00      //
    0x13, 0x00      //
    0x14, 0x00      //
    0x15, 0x00      //


    0x16, 0x00      // Set up rate converter
    0x17, 0x00      //
    0x18, 0x80      //
    0x19, 0x00      //
    0x1A, 0x00      //
    0x1B, 0x70      //


    0x1C, 0x3F      // Set up BPF center frequency
    0x1D, 0x3B      //


    0x20, 0xC4      // Set up interface
    0x21, 0x78      //
    0x22, 0x2F      //
    0x23, 0x00      //


    0x25, 0x80      // Set up channel gain
    0x26, 0x00      //
    0x27, 0x00      //
    0x28, 0x00      //


    0x29, 0x00      // Set up spectral invert


    0x3C, 0x00      // Set up full-scale current
    0x3D, 0x02      //


    0x05, 0x01      // Set up Channel 0 (Only)


I have setup parameter with use of register 0x1E and 0x24.


The register LTNC[2:0]   is 0x00 (on register 0x21)
The register DSCPHZ[3:0] is 0x00 (on register 0x23)
The register SNCPHZ[3:0] is 0x00 (on register 0x23)


Offset out is made with FPGA to setup-holt timing.


I checked the setup-hold time with an oscilloscope and all seems ok.


Now the problems begin. I have place out signal from DDS with this
output aspect on bus :


AD9789 Multi Channel.PNG


But no output on DAC RF why ?!?!?!?


After some test I have inserted a variable latency of the I / Q data
to delay the data of x DCO cycle. after inserting some delays I got
this configuration that works. On output of DAC I have RF signal.


AD9789 Multi Channel working.PNG

Why it is necessary to introduce this latency with my configuration ?


I tried to activate the other channels (CH1, CH2 and CH3) singly and are arranged as in previous figure.


How is this possible ?


Where is that wrong ?


Thanks very much.