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AD9361 Xilinx files cannot build correctly

Question asked by htorke on May 25, 2016
Latest reply on Jul 26, 2016 by CsomI

I have Vivado 2015.4 on my workstation, and am trying to build the AD9361 HDL reference to see how you are interfacing with the Zynq-7000 processor in the FMCOMMS2 project. I have downloaded the branch HDL-HDL_2015_r2 from your Git repository, and want to build the project in Vivado.

 

The problem which is occurring is this: When I navigate to the library folder for the AD9361 and try to build the IP core, I receive an error "ERROR: This library requires Vivado 2014.4.1." which seems odd, as I would expect the newer version to be compatible with the 2015 version of Vivado. However, I have Vivado 2014.4 on another computer, so I tried unpacking that. When I tried opening a project in 2014.4, I received the error "ERROR: This library requires Vivado 2015.2.1."

 

After this, I tried instead cloning a different branch, HDL-HDL_2014_r1, and opening that in Vivado 2014.4, which gave me an error saying that I needed 2015.2. When I tried opening axi_ad9361_ip.tcl using Vivado 2015.4, I finally got the IP core to open, but with the following:

 

source axi_ad9361_ip.tcl # source ../scripts/adi_env.tcl ## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]] ## set ad_phdl_dir $ad_hdl_dir ## if [info exists ::env(ADI_HDL_DIR)] { ##   set ad_hdl_dir $::env(ADI_HDL_DIR) ## } ## if [info exists ::env(ADI_PHDL_DIR)] { ##   set ad_phdl_dir $::env(ADI_PHDL_DIR) ## } # source $ad_hdl_dir/library/scripts/adi_ip.tcl ## if {![info exists REQUIRED_VIVADO_VERSION]} { ##   set REQUIRED_VIVADO_VERSION "2015.2.1" ## } ## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} { ##   set IGNORE_VERSION_CHECK 1 ## } elseif {![info exists IGNORE_VERSION_CHECK]} { ##   set IGNORE_VERSION_CHECK 0 ## } ## proc adi_ip_create {ip_name} { ## ##   global ad_hdl_dir ##   global ad_phdl_dir ##   global REQUIRED_VIVADO_VERSION ##   global IGNORE_VERSION_CHECK ## ##   if {!$IGNORE_VERSION_CHECK && [string compare [version -short] $REQUIRED_VIVADO_VERSION] != 0} { ##     return -code error [format "ERROR: This library requires Vivado %s." $REQUIRED_VIVADO_VERSION] ##   } ## ##   create_project $ip_name . -force ## ##   set lib_dirs $ad_hdl_dir/library ##   if {$ad_hdl_dir ne $ad_phdl_dir} { ##     lappend lib_dirs $ad_phdl_dir/library ##   } ## ##   set_property ip_repo_paths $lib_dirs [current_fileset] ##   update_ip_catalog ## ##   set proj_dir [get_property directory [current_project]] ##   set proj_name [get_projects $ip_name] ## } ## proc adi_ip_files {ip_name ip_files} { ## ##   set proj_fileset [get_filesets sources_1] ##   add_files -norecurse -scan_for_includes -fileset $proj_fileset $ip_files ##   set_property "top" "$ip_name" $proj_fileset ## } ## proc adi_ip_constraints {ip_name ip_constr_files {processing_order late}} { ## ##   set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] ##   foreach f_name $ip_constr_files { ##     ipx::add_file $f_name $proj_filegroup ##     set_property type xdc [ipx::get_files $f_name -of_objects $proj_filegroup] ##     set_property processing_order $processing_order [ipx::get_files $f_name -of_objects $proj_filegroup] ##   } ## } ## proc adi_ip_ttcl {ip_name ip_constr_files} { ## ##   set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] ##   set f [ipx::add_file $ip_constr_files $proj_filegroup] ##   set_property -dict [list \ ##     type ttcl \ ##   ] $f ## } ## proc adi_ip_bd {ip_name ip_bd_files} { ##   set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] ##   if {$proj_filegroup == {}} { ##     set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] ##   } ##   set f [ipx::add_file $ip_bd_files $proj_filegroup] ##   set_property -dict [list \ ##     type tclSource \ ##   ] $f ## } ## proc adi_ip_properties {ip_name} { ## ##   ipx::package_project -root_dir . ##   ipx::remove_memory_map {s_axi} [ipx::current_core] ##   ipx::add_memory_map {s_axi} [ipx::current_core] ##   set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] ## ##   ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] ##   set_property range {65536} [ipx::get_address_blocks axi_lite \ ##     -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] ## ##   set_property vendor {analog.com} [ipx::current_core] ##   set_property library {user} [ipx::current_core] ##   set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core] ##   set_property vendor_display_name {Analog Devices} [ipx::current_core] ##   set_property company_url {www.analog.com} [ipx::current_core] ## ##   set_property supported_families \ ##     {{kintexu}    {Pre-Production} \ ##      {virtexu}    {Pre-Production} \ ##      {virtex7}    {Production} \ ##      {qvirtex7}   {Production} \ ##      {kintex7}    {Production} \ ##      {kintex7l}   {Production} \ ##      {qkintex7}   {Production} \ ##      {qkintex7l}  {Production} \ ##      {artix7}     {Production} \ ##      {artix7l}    {Production} \ ##      {aartix7}    {Production} \ ##      {qartix7}    {Production} \ ##      {zynq}       {Production} \ ##      {qzynq}      {Production} \ ##      {azynq}      {Production}} \ ##   [ipx::current_core] ## } ## proc adi_ip_properties_lite {ip_name} { ## ##   ipx::package_project -root_dir . ## ##   set_property vendor {analog.com} [ipx::current_core] ##   set_property library {user} [ipx::current_core] ##   set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core] ##   set_property vendor_display_name {Analog Devices} [ipx::current_core] ##   set_property company_url {www.analog.com} [ipx::current_core] ## ##   set_property supported_families \ ##     {{kintexu}    {Pre-Production} \ ##      {virtexu}    {Pre-Production} \ ##      {virtex7}    {Production} \ ##      {qvirtex7}   {Production} \ ##      {kintex7}    {Production} \ ##      {kintex7l}   {Production} \ ##      {qkintex7}   {Production} \ ##      {qkintex7l}  {Production} \ ##      {artix7}     {Production} \ ##      {artix7l}    {Production} \ ##      {aartix7}    {Production} \ ##      {qartix7}    {Production} \ ##      {zynq}       {Production} \ ##      {qzynq}      {Production} \ ##      {azynq}      {Production}} \ ##   [ipx::current_core] ## } ## proc adi_set_ports_dependency {port_prefix dependency} { ##     foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { ##         set_property ENABLEMENT_DEPENDENCY $dependency $port ##     } ## } ## proc adi_set_bus_dependency {bus prefix dependency} { ##     set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] ##     adi_set_ports_dependency $prefix $dependency ## } ## proc adi_add_port_map {bus phys logic} { ##     set map [ipx::add_port_map $phys $bus] ##     set_property "PHYSICAL_NAME" $phys $map ##     set_property "LOGICAL_NAME" $logic $map ## } ## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { ##     set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] ## ##     set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus ##     set_property "BUS_TYPE_VLNV" $bus_type $bus ##     set_property "INTERFACE_MODE" $mode $bus ## ##     foreach port_map $port_maps { ##         adi_add_port_map $bus {*}$port_map ##     } ## } ## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { ##     set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] ##     set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] ##     set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] ##     set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf ##     set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf ##     set_property display_name $clock_inf_name $clock_inf ##     set clock_map [ipx::add_port_map "CLK" $clock_inf] ##     set_property physical_name $clock_signal_name $clock_map ## ##     set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] ##     set_property value $bus_inf_name $assoc_busif ## ##     if { $reset_signal_name != "" } { ##         set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] ##         set_property value $reset_signal_name $assoc_reset ## ##         set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] ##         set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] ##         set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf ##         set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf ##         set_property display_name $reset_inf_name $reset_inf ##         set_property interface_mode $reset_signal_mode $reset_inf ##         set reset_map [ipx::add_port_map "RST" $reset_inf] ##         set_property physical_name $reset_signal_name $reset_map ## ##         set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] ##         set_property value "ACTIVE_LOW" $reset_polarity ##     } ## } ## proc adi_ip_add_core_dependencies {vlnvs} { ##     foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { ##         foreach vlnv $vlnvs { ##             ipx::add_subcore $vlnv $file_group ##         } ##     } ## } ## proc adi_if_define {name} { ## ##   ipx::create_abstraction_definition ADI user ${name}_rtl 1.0 ##   ipx::create_bus_definition ADI user $name 1.0 ## ##   set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] ##   set_property xml_file_name ${name}.xml [ipx::current_busdef] ##   set_property bus_type_vlnv ADI:user:${name}:1.0 [ipx::current_busabs] ## ##   ipx::save_abstraction_definition [ipx::current_busabs] ##   ipx::save_bus_definition [ipx::current_busdef] ## } ## proc adi_if_ports {dir width name {type none}} { ## ##   ipx::add_bus_abstraction_port $name [ipx::current_busabs] ##   set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] ##   set_property master_presence required $m_intf ##   set_property slave_presence  required $m_intf ##   set_property master_width $width $m_intf ##   set_property slave_width  $width $m_intf ## ##   set m_dir "in" ##   set s_dir "out" ##   if {$dir eq "output"} { ##     set m_dir "out" ##     set s_dir "in" ##   } ## ##   set_property master_direction $m_dir $m_intf ##   set_property slave_direction  $s_dir $m_intf ## ##   if {$type ne "none"} { ##     set_property is_${type} true $m_intf ##   } ## ##   ipx::save_bus_definition [ipx::current_busdef] ##   ipx::save_abstraction_definition [ipx::current_busabs] ## } ## proc adi_if_infer_bus {if_name mode name maps} { ## ##   ipx::add_bus_interface $name [ipx::current_core] ##   set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] ##   set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if ##   set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if ##   set_property interface_mode $mode $m_bus_if ## ##   foreach map $maps  { ##     set m_maps [regexp -all -inline {\S+} $map] ##     lassign $m_maps p_name p_map ##     ipx::add_port_map $p_name $m_bus_if ##     set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] ##   } ## } # adi_ip_create axi_ad9361 ERROR: This library requires Vivado 2015.2.1.     while executing "adi_ip_create axi_ad9361"     (file "axi_ad9361_ip.tcl" line 6) cd cd desktop/hdl-hdl_2014_r1/library/axi_ad9361 source axi_ad9361_ip.tcl # source ../scripts/adi_env.tcl ## set ad_hdl_dir  "../.." ## set ad_phdl_dir "../.." ## if [info exists ::env(ADI_HDL_DIR)] { ##   set ad_hdl_dir $::env(ADI_HDL_DIR) ## } ## if [info exists ::env(ADI_PHDL_DIR)] { ##   set ad_phdl_dir $::env(ADI_PHDL_DIR) ## } # source $ad_hdl_dir/library/scripts/adi_ip.tcl ## proc adi_ip_create {ip_name} { ## ##   create_project $ip_name . -force ## ##   set proj_dir [get_property directory [current_project]] ##   set proj_name [get_projects $ip_name] ## } ## proc adi_ip_files {ip_name ip_files} { ## ##   set proj_fileset [get_filesets sources_1] ##   add_files -norecurse -scan_for_includes -fileset $proj_fileset $ip_files ##   set_property "top" "$ip_name" $proj_fileset ## } ## proc adi_ip_constraints {ip_name ip_constr_files} { ## ##   set proj_filegroup [ipx::get_file_group xilinx_verilogsynthesis [ipx::current_core]] ##   ipx::add_file $ip_constr_files $proj_filegroup ##   set_property type {{xdc}} [ipx::get_file $ip_constr_files $proj_filegroup] ##   set_property library_name {} [ipx::get_file $ip_constr_files $proj_filegroup] ## } ## proc adi_ip_properties {ip_name} { ## ##   ipx::package_project -root_dir . ##   ipx::remove_memory_map {s_axi} [ipx::current_core] ##   ipx::add_memory_map {s_axi} [ipx::current_core] ##   set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interface s_axi [ipx::current_core]] ## ##   ipx::add_address_block {axi_lite} [ipx::get_memory_map s_axi [ipx::current_core]] ##   set_property range {65536} [ipx::get_address_block axi_lite \ ##     [ipx::get_memory_map s_axi [ipx::current_core]]] ## ##   set_property vendor {analog.com} [ipx::current_core] ##   set_property library {user} [ipx::current_core] ##   set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core] ##   set_property vendor_display_name {Analog Devices} [ipx::current_core] ##   set_property company_url {www.analog.com} [ipx::current_core] ## ##   set_property supported_families \ ##     {{kintexu}    {Pre-Production} \ ##      {virtexu}    {Pre-Production} \ ##      {virtex7}    {Production} \ ##      {qvirtex7}   {Production} \ ##      {kintex7}    {Production} \ ##      {kintex7l}   {Production} \ ##      {qkintex7}   {Production} \ ##      {qkintex7l}  {Production} \ ##      {artix7}     {Production} \ ##      {artix7l}    {Production} \ ##      {aartix7}    {Production} \ ##      {qartix7}    {Production} \ ##      {zynq}       {Production} \ ##      {qzynq}      {Production} \ ##      {azynq}      {Production}} \ ##   [ipx::current_core] ## } ## proc adi_ip_properties_lite {ip_name} { ## ##   ipx::package_project -root_dir . ## ##   set_property vendor {analog.com} [ipx::current_core] ##   set_property library {user} [ipx::current_core] ##   set_property taxonomy {{/AXI_Infrastructure}} [ipx::current_core] ##   set_property vendor_display_name {Analog Devices} [ipx::current_core] ##   set_property company_url {www.analog.com} [ipx::current_core] ## ##   set_property supported_families \ ##     {{kintexu}    {Pre-Production} \ ##      {virtexu}    {Pre-Production} \ ##      {virtex7}    {Production} \ ##      {qvirtex7}   {Production} \ ##      {kintex7}    {Production} \ ##      {kintex7l}   {Production} \ ##      {qkintex7}   {Production} \ ##      {qkintex7l}  {Production} \ ##      {artix7}     {Production} \ ##      {artix7l}    {Production} \ ##      {aartix7}    {Production} \ ##      {qartix7}    {Production} \ ##      {zynq}       {Production} \ ##      {qzynq}      {Production} \ ##      {azynq}      {Production}} \ ##   [ipx::current_core] ## } ## proc adi_set_ports_dependency {port_prefix dependency} { ##     foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { ##         set_property ENABLEMENT_DEPENDENCY $dependency $port ##     } ## } ## proc adi_set_bus_dependency {bus prefix dependency} { ##     set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interface $bus [ipx::current_core]] ##     adi_set_ports_dependency $prefix $dependency ## } ## proc adi_add_port_map {bus phys logic} { ##     set map [ipx::add_port_map $phys $bus] ##     set_property "PHYSICAL_NAME" $phys $map ##     set_property "LOGICAL_NAME" $logic $map ## } ## proc adi_add_bus {bus_name bus_type mode port_maps} { ##     set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] ##     if { $bus_type == "axis" } { ##         set abst_type "axis_rtl" ##     } elseif { $bus_type == "aximm" } { ##         set abst_type "aximm_rtl" ##     } else { ##         set abst_type $bus_type ##     } ## ##     set_property "ABSTRACTION_TYPE_LIBRARY" "interface" $bus ##     set_property "ABSTRACTION_TYPE_NAME" $abst_type $bus ##     set_property "ABSTRACTION_TYPE_VENDOR" "xilinx.com" $bus ##     set_property "ABSTRACTION_TYPE_VERSION" "1.0" $bus ##     set_property "BUS_TYPE_LIBRARY" "interface" $bus ##     set_property "BUS_TYPE_NAME" $bus_type $bus ##     set_property "BUS_TYPE_VENDOR" "xilinx.com" $bus ##     set_property "BUS_TYPE_VERSION" "1.0" $bus ##     set_property "CLASS" "bus_interface" $bus ##     set_property "INTERFACE_MODE" $mode $bus ## ##     foreach port_map $port_maps { ##         adi_add_port_map $bus {*}$port_map ##     } ## } ## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""}} { ##     set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] ##     set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] ##     set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] ##     set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf ##     set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf ##     set_property display_name $clock_inf_name $clock_inf ##     set clock_map [ipx::add_port_map "CLK" $clock_inf] ##     set_property physical_name $clock_signal_name $clock_map ## ##     set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] ##     set_property value $bus_inf_name $assoc_busif ## ##     if { $reset_signal_name != "" } { ##         set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] ##         set_property value $reset_signal_name $assoc_reset ## ##         set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] ##         set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] ##         set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf ##         set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf ##         set_property display_name $reset_inf_name $reset_inf ##         set reset_map [ipx::add_port_map "RST" $reset_inf] ##         set_property physical_name $reset_signal_name $reset_map ## ##         set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] ##         set_property value "ACTIVE_LOW" $reset_polarity ##     } ## } # adi_ip_create axi_ad9361 INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2015.4/data/ip'. # adi_ip_files axi_ad9361 [list \ #   "$ad_hdl_dir/library/common/ad_rst.v" \ #   "$ad_hdl_dir/library/common/ad_lvds_clk.v" \ #   "$ad_hdl_dir/library/common/ad_lvds_in.v" \ #   "$ad_hdl_dir/library/common/ad_lvds_out.v" \ #   "$ad_hdl_dir/library/common/ad_mul.v" \ #   "$ad_hdl_dir/library/common/ad_pnmon.v" \ #   "$ad_hdl_dir/library/common/ad_dds_sine.v" \ #   "$ad_hdl_dir/library/common/ad_dds_1.v" \ #   "$ad_hdl_dir/library/common/ad_dds.v" \ #   "$ad_hdl_dir/library/common/ad_datafmt.v" \ #   "$ad_hdl_dir/library/common/ad_dcfilter.v" \ #   "$ad_hdl_dir/library/common/ad_iqcor.v" \ #   "$ad_hdl_dir/library/common/up_axi.v" \ #   "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ #   "$ad_hdl_dir/library/common/up_xfer_status.v" \ #   "$ad_hdl_dir/library/common/up_clock_mon.v" \ #   "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ #   "$ad_hdl_dir/library/common/up_drp_cntrl.v" \ #   "$ad_hdl_dir/library/common/up_adc_common.v" \ #   "$ad_hdl_dir/library/common/up_adc_channel.v" \ #   "$ad_hdl_dir/library/common/up_dac_common.v" \ #   "$ad_hdl_dir/library/common/up_dac_channel.v" \ #   "axi_ad9361_dev_if.v" \ #   "axi_ad9361_rx_pnmon.v" \ #   "axi_ad9361_rx_channel.v" \ #   "axi_ad9361_rx.v" \ #   "axi_ad9361_tx_channel.v" \ #   "axi_ad9361_tx.v" \ #   "axi_ad9361.v" ] # adi_ip_properties axi_ad9361 CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_mul.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_dds_sine.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_pnmon.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_dds_1.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_xfer_cntrl.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_xfer_status.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_rst.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_dds.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_datafmt.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_dcfilter.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_iqcor.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_clock_mon.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_delay_cntrl.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_drp_cntrl.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_adc_channel.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_dac_channel.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_lvds_clk.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_lvds_in.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_lvds_out.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_adc_common.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_dac_common.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_axi.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_mul.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_dds_sine.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_pnmon.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_dds_1.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_xfer_cntrl.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_xfer_status.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_rst.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_dds.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_datafmt.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_dcfilter.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_iqcor.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_clock_mon.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_delay_cntrl.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_drp_cntrl.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_adc_channel.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_dac_channel.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_lvds_clk.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_lvds_in.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/ad_lvds_out.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_adc_common.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_dac_common.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. CRITICAL WARNING: [IP_Flow 19-459] IP file 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/common/up_axi.v' appears to be outside of the project area 'C:/Users/e338162/desktop/hdl-hdl_2014_r1/library/axi_ad9361'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory. INFO: [IP_Flow 19-2228] Inferred bus interface "s_axi" of definition type "xilinx.com:interface:aximm:1.0". INFO: [IP_Flow 19-2228] Inferred bus interface "s_axi_aresetn" of definition type "xilinx.com:signal:reset:1.0". INFO: [IP_Flow 19-2228] Inferred bus interface "clk" of definition type "xilinx.com:signal:clock:1.0". INFO: [IP_Flow 19-2228] Inferred bus interface "s_axi_aclk" of definition type "xilinx.com:signal:clock:1.0". INFO: [IP_Flow 19-2228] Inferred bus interface "s_axi_aresetn" of definition type "xilinx.com:signal:reset:1.0". INFO: [IP_Flow 19-2228] Inferred bus interface "clk" of definition type "xilinx.com:signal:clock:1.0". INFO: [IP_Flow 19-2228] Inferred bus interface "delay_clk" of definition type "xilinx.com:signal:clock:1.0". INFO: [IP_Flow 19-2228] Inferred bus interface "l_clk" of definition type "xilinx.com:signal:clock:1.0". INFO: [IP_Flow 19-2228] Inferred bus interface "s_axi_aclk" of definition type "xilinx.com:signal:clock:1.0". WARNING: command 'get_bus_interface' will be removed in the 2015.3 release, use 'get_bus_interfaces' instead WARNING: command 'get_memory_map' will be removed in the 2015.3 release, use 'get_memory_maps' instead WARNING: command 'get_memory_map' will be removed in the 2015.3 release, use 'get_memory_maps' instead WARNING: command 'get_address_block' will be removed in the 2015.3 release, use 'get_address_blocks' instead WARNING: command 'get_bus_interface' will be removed in the 2015.3 release, use 'get_bus_interfaces' instead No bus_interface found that matches 's_axi_signal_clock'     while executing "error "No bus_interface found that matches 's_axi_signal_clock'""     ("uplevel" body line 1)     invoked from within "uplevel 1 "error \"No $singular found that matches '$name'\"""     invoked from within "if { $res eq "" } {       uplevel 1 "error \"No $singular found that matches '$name'\""     }"     (procedure "::ipx::utils::get_single_obj" line 21)     invoked from within "::ipx::utils::get_single_obj bus_interface {} {*}$args"     (procedure "ipx::get_bus_interface" line 1)     invoked from within "ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]"     invoked from within "ipx::get_port_map CLK \   [ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]"     invoked from within "set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \   [ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]]"     (file "axi_ad9361_ip.tcl" line 40) update_compile_order -fileset sim_1

 

 

As you can see, there are several critical errors that make methink the IP core is not properly built. Additionally when I tried building the fmcomm2 project I recieved the error "ERROR: [BD 5-216] VLNV <xilinx.com:ip:processing_system7:5.3> is not supported for the current part. The latest supported version for this part is:5.5.

 

How can I obtain the HDL Vivado project for the FMcomms2 project used to connect the FMCOMMS3 board to a zc706 Xilinx board, as described here:AD9361 HDL Reference Designs [Analog Devices Wiki]  ?

Outcomes