Hi, ADI Support Team
I have a question about ADAU1977.
When the CLK_S bit PLL_CONTROL register is set to “1:LRCLK”, which timing does LRCLK signal have to input?
In my system, the PLL_LOCK bit (Bit7) of PLL_CONTROL register indicate “1:PLL Locked” in spite of without LRCLK input.
Is it correct behavior?
I guessed that to become "PLL Locked" LRCLK input is needed.
For your reference, my sequence is as follows.
- Write 0x01 (Power-Up) to M_POWER register
- Write 0x51 (LRCLK mode) to PLL_CONTROL register *In this timing, there is not LRCLK input.
- Read PLL_CONTROL register as 0xD1 (PLL Locked)
Thanks in advance,