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AD9675 programming and JESD204B lane rate

Question asked by tonyle on May 23, 2016
Latest reply on Mar 12, 2018 by zimou13

I'm trying to debug the JESD204B link between two AD9675's and our FPGA receiver (Xilinx 7 series). We are not achieving sync between the devices (as indicated by the FPGA holding SYNCINB low). I'd like to make sure I've calculated the ADC lane rate correctly and that the programming sequence is correct.

 

The FPGA core is configured to receive data at 2.0 Gbps on each lane, and I've configured the ADCs in such a way that I believe the lane rate should be 2.0 Gbps. As far as I can tell, the data sheet (Rev. A) doesn't specifically give a formula for thisr; rather, the specification for IDRVDD on page 6 implies that the data rate in a four-lane configuration is 20 times the CLK speed for Modes III and IV (assuming the RF decimator is turned on). We are using a 100 MHz clock which is how I inferred 2.0 Gbps. Am I correct?

 

Here also is the ADC programming sequence. I'm especially curious about 0x181, the PLL N-divider setting. There isn't any information about this setting beyond the short entry in the register table.

 

Thanks for your help!

 

Address

Data

Operation

0x142

0x01

Power down JESD204B link

0x000

0x3C

Initiate SPI reset

0x002

0x30

Set speed mode to 125 MSPS

0x0FF

0x01

Enable speed mode change

0x004

0x0F

Set local registers to all channels

0x005

0x3F

Set local registers to all channels

0x113

0x04

Enable RF decimator and low-bandwidth filter, enable high-pass filter

0x011

0x06

Set LNA gain = 21.6 dB, GAIN± pins enabled, and PGA gain = 24 dB

0xF00

0xFF

Continuous run mode enable; do not power down channels (POWER_STOP LSB)

0xF01

0x7F

Continuous run mode enable; do not power down channels (POWER_STOP MSB)

0xF02

0x00

Power up all channels 0 clock cycles after TX_TRIG± signal assertion (POWER_START LSB)

0xF03

0x80

Digital high-pass bypassed (POWER_START MSB)

0x10C

0x00

Set index profile (required after profile memory writes)

0x014

0x01

Set output data format

0x008

0x00

Chip run (TGC mode)

0x021

0x12

16-bit, four-lane mode

0x199

0x80

Enables automatic serializer/deserializer (SERDES) sample clock counter

0x188

0x01

Enable start code identifier

0x18B

0x27

Set start code MSB

0x18C

0x72

Set start code LSB

0x150

0x83

JESD204B scrambler enabled and four-lane configuration (L = 4)

0x182

0x82

Automatically configures PLL

0x181

0x01

PLL N-divider = ÷10

0x10C

0x20

Set SPI TX_TRIG and index profile

0x00F

0xB0

Set antialiasing LPF cutoff frequency to 6.25 MHz (0.75/6 × 50 MHz), low bandwidth mode

0x02B

0x43

Set analog HPF cutoff frequency to 2.083 MHz (LPF cutoff/3.0), tune filters

0x186

0xAA

Disable continuous data resync (continuous data resync is not recommended during real-time scanning; one time data resync is sufficient)

0x142

0x14

Power up JESD204B link, ILAS enabled, lane sync enabled

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