Our requirement is to use the AD9361 in CMOS mode since the existing FPGA design can support only CMOS mode.
We have made a custom made AD9361 board with the buffers on Data & CLK lines which needs to be tested with the ZYNQ reference design.
We have modified the reference design and converted the LVDS interface to CMOS made,during booting time we have noticed TX &RX tuning fail and also IIO scope didn't get enabled.
I have attached here the boot up message and clk and data wave from at @3.84MHz clk.
We have noticed Data and clk were quite ok at lower CLK frequency, we have modified the dts file with 3.84MHz clk rates but we have failed to get it and the system starts with the default clk rates of 61MHz.
Apart from these issues we are not sure why the IIO scope didnt get enabled.