AnsweredAssumed Answered

The output of AD9914 is not right

Question asked by GYP on May 19, 2016
Latest reply on Jun 2, 2016 by GYP

Hi

I am sorry to interrupt you but  I have some questions and I need your help when I'm using the FPGA  to control the DDS AD9914.

1、I use the internal PLL of AD9914, I am using 50Mhz signal whose power is 4dbm and Vpp is1.85V as  the reference  clock, and I set N=25 ,so the system clock is 2.5GHz,but the SYNC_CLK output is not 104.166MHz,the figure is attached.

The register setting is below  and I use parallel timing and profile mode.

F0=0 ,F1=0,F2=0,F3=0, PS0=0,PS1=0,PS2=0,D0/PWD=0,EXT_PWR_DWN=0,issue masterreset ,

addess                               data

ox0A                                  ox04

ox03                                   ox01

update

ox03                                   ox00

update

ox05                                  ox08

ox06                                   ox80

ox08                                   ox1C

ox09                                   ox19

ox0F                                   ox01

update

ox0F                                   ox00

update

ox2C                                  oxBA

ox2D                                  ox49

ox2E                                  ox0C

ox2F                                   ox02    

other registers are using the default value

so as the profile register set,I should  get output of 20MHz,but  the frequency is not right,the result is below.

I think the reason is that the PLL is locked not right,but I don't know what to do.and how long should  I set  PLL cal.   

2、  when I design the PCB for the AD9914 , I miss the connection of the pll loop-filter to ground,other components are the same with the evaluation board schematic diagram ,so I use a jumper wire when testing, but I don't know whether  it influence much.

Sincerely looking forward to your reply.

Best regards,

 

 

SYNC-CLk output

SYNC_CLK.bmp

 

DAC Output

DAC,Output.bmp

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