I have question on the general SPORT interface operation, specifically to the use of late frame sync signal.
The question is, if i configure the SPORT receive port to receive data with an edge triggered, external late frame sync signal, does the frame sync signal width matter?
take the diagram below, where the falling edge of the external late frame sync is used for framing the data, and in this example the data is 32 bits.
because the frame sync signal is configured to be edge triggered, does it matter where the rising edge of the frame sync signal is?
What happens if the rising edge occurred before the completion of receiving the word, as in the case of signal DATA B? Would SPORT buffer keep receiving the data?
and what happens if the rising edge occured a few SCLK cycles after the completion of receiving the word, as in the case of signal DATA C? Would SPORT receiving buffer stop taking data after SLEN counter has reached zero?
Does all the ADI DSPs behaves the same with the case described above? And do most of them support inverted, edge detect, external late frame sync signal on the SPORT receive port?
I was reading ADSP-SC58x SHARC Processor Hardware Reference manual, and on Page 1369, when it talked about late frame sync, it states: "Externally generated frame syncs are only checked during the first bit."
how should i interpret this line? does it apply to level detect frame sync only?