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ADSPBF-706, SEC, Interrupt priorities

Question asked by Dimitry. on May 17, 2016
Latest reply on Jun 17, 2016 by Dimitry.

Hello,

I have a question about SEC in ADSPBF-706. The same question was asked here: https://ez.analog.com/message/150911#comment-150911 and I made the next conclusion:

For example, I activate two interrupts TMR1 (SID = 12) and PINT0 (SID = 20). When the TMR1 interrupt is asserted , while running the PINT0 ISR, immediately PC calls the TMR1 ISR, even the PINT0 ISR is not completed.

 

But in the practice I got this result: Controller executes PINT0 ISR, finished it and only after this goes to the high priority interrupt TMR1 (with more higher ID in  ADSP-BF70x Interrupt List). In the Source Control Register all priority levels are set by default = 0.

     Started PINT0 ISR –> Asserted TMR1 ISR –> Finished PINT0 ISR –> Started TMR1 ISR

 

After priorities are set manually, SEC became to work correctly:

     Started PINT0 ISR –> Asserted TMR1 ISR –> Finished TMR1 ISR –> Continued PINT0 ISR

Could you tell me please it’s necessary to set up manually all interrupt priorities with the Source Control Registers, even if in Hardware Manual is written:

“… if SID 0, SID 1, and SID 2 are all pending and have the same priority setting, the SCI chooses SID 0 as the highest priority pending system interrupt source”

?

 

Thank you,

Dmitry

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