I'm configuring an ADV7181C with an FPGA for 1027x768 12-bit DDR. I had the FPGA I2C master design working with the I2C and ADV7181 video output connecting ADV7181C and FPGA development boards. Now, with our prototype board, I seem to get no meaningful data. The syncs are making it through. I saw, in a much earlier thread about an ADV7181C in 640x480 mode, that address 12 = 80 and B1 = 9C are good signs. Our design is returning 80 and 92. I do not know the significance of the 9C vs. 92 difference. I'm using the script from ADV7181C_ADV7181C@_ADV7341-VER.3.2c.txt.
All of the script-written registers read back what was written except for F6 which was written with 69, but reads back 3B. In the manual, F6 is specified as reserved, so I don't know what the significance of the difference is.
There are curious things about the script. Registers E0, ADI Control, and 52, CSC_1, are written as 80 and 46 respectively. Then latter written again as 00 and 80. They read back after configuration as 00 and 80 (the same as the second writes). E0 is reserved, default 0. 52 default is 80.
We've repeatedly gone over the schematic to verify that it matches the development kit. The unit that the board is in has both front and back planes, so there is no way to probe it directly. We've tacked on a few wires. The signal integrity of them is good. We are able to check the video into the Altera FPGA using SignalTap. The DDR data changes infrequently and is pretty much the same from one active line to the next. The non-active lines are different from the active ones.
Are there other status registers to check in CP mode? Any other ideas?
Thanks in advance,