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Too many SPI clock cycles

Question asked by t8102 on Jul 20, 2011
Latest reply on Jul 22, 2011 by t8102

I am currently trying to read an AD7980 16 bit ADC using the SPI port on a Shark ADSP-21479. The shark is the master

I am using TIMOD=00 (initiate transfer on RX read), because I want an interrupt to be generated when the receive buffer has a word in it. However for some reason the shark does not seem to be generating the correct number of SCLK cycles. With the word length is set to WL16 in the SPICTRL register I am getting 48 clock cycles generated instead of the expected 16. If I set the word length to WL8, the shark generated 24 clock cycles.

 

If I set TIMOD=01 (initiate transfer on TX data write) the correct number of clock cycles are generated.

 

Any advice would be greatly welcomed.

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