Dear Analog Devices
I found a lot of PFD(40MHz)+ADC clock(61.44MHz) harmonics at RF output.
This spurs only show up when I enable BBPLL.
please see the attached picture.
How does this happen?
BBPLL is responsible for generating all digital clocks on the device. What you are seeing is spurious energy from various digital clocks in the device.
Is there any possible configuration that may suppress the noise level?
Using the device in LVDS mode, isolating digital supplies, supply bypassing, using good layout practices and of course filtering (especially for spectral content at higher frequencies) all help with reducing spurious content at the Tx output.
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