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ADV7281 configuration

Question asked by ErichNast on May 16, 2016
Latest reply on May 17, 2016 by Rob.Analog

We have a system using a ADV7281WBCPZ video decoder. The input to the device should be standard PAL class B interlaced, 625 lines per frame (complying with STANAG 3350 class B). The required output is fed to a DLP controller with an 8-bit YCbCr 4:2:2 data bus and pixel clock. The bus is compatible with the 8-bit ITU-R BT. 656 interface standard. Pixel are is nominal 27 MHz.

 

Is the ADV7281 capable of this, and if so, would Analog Devices be able to provide us with the required configuration settings for the device? Furthermore, how do we control the output resolution of the device?

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