AnsweredAssumed Answered

BF506 Sport interface SCLK stop-mode?

Question asked by MarienVermeulen on Jul 20, 2011
Latest reply on Aug 7, 2011 by MarienVermeulen

I have made twoo screen shots:

Ch1= SCLK  (from Sport to ADC)

Ch2= Dout  (from ADC to Sport)

Ch3= DRDY  (from ADC to Sport)

 

BMP_201172019925.bmp: 

DRDY falling edge just before rising SCLK.   ADC sees this als teh first rissing edge and shifts the next data bit.

The Sport interface doesn't.  so we mis de MSB bit of tha sample.

 

BMP_201172019933.bmp: 

DRDY falling edge after rising SCLK.  

This gives a correct data sample

 

 

Description:

I interface the ADS1271 (TI) to the SPORT interface. SCLK to SPORT0_RX_serial CLK, Dout to Pri_RX_Data, DRDY to RX_frameSync.

I can read the 24bit continuously; the sports reads out the 24bit after each DRDY pulse. This puls in low active.

The ADC runs at 24,576MHz clock. the BF506 at 25.0MHz.

The problem: The data has bit shift error. the first data bit is sampled once 1 time, then not. So I get a data valus shift (1 bit to the left).

This seems to be due to the SCLK clock is running all the time. If DRDY falling edge is after the rissing SCK, then the ADC data is correct. When the falling DRDY edge is just before the rissing SCLK edge; the first databit is not sampled bij the SPORT. The ADC has detected the rissing SCLK, so will shift the next bit to Dout.

As my DSP and ADC do not share the same oscillator the DRDY edge and SCLK edge will interfere. setup times will become/are the problem.

Actually the SCLK must start running as soon as the DRDY edge is detected, and stop after 24 bits.

 

Can I set the SPORT in some kind of stop mode?

The SCLK clock may start running after the frame sync.

Outcomes