I am using an FPGA to construct an ADPLL with a central frequency equal to 32kHz. I have to continuously write the tuning word to the frequency register , according to the data I am getting from the loop filter. I am using the mode where the whole 28 bit word is written into the frequency register.
But the data is written in two write commands sending 14 bit of data and 2 bits of the register address at a time. While writing the data to register FSYNC has to be taken low. Here is the timing diagram.
My question is when I am performing the write operation on the frequency register, for how long do I have to make FSYNC high after writing the first 16 bits of the 32 bit of data.