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What is the ad9680's default I/Q byte order?

Question asked by -2dbc on May 13, 2016
Latest reply on Sep 9, 2016 by charlyelkhoury
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I'm using your default FPGA reference design and no-OS driver codes(ramp test mode). I can see samples on ILA.

Ramp data looks like this: 1,2,3,4,5,6....  I had expected repeating values but there is no duplicate value.

I also examined your block design.

adc_data_0[63:0] means Channel 1 and adc_data_1[63:0] means Channel 2.

I could not understand which bytes are I and which ones are Q.

 

Thanks in advance.

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