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How do we get deteriminstic latency from the AD9690?

Question asked by timothy.starr on May 13, 2016
Latest reply on May 13, 2016 by TonyM


We are planning on using the AD9690 in subclass 1 operation for JESD204B.  The implication is the use of the SYSREF input to the ADC which must be well controlled and synchronized with the sample clock.   We need to “trigger” the ADC at such a point that we can accurately measure the sample arrival time.  We sample for 50 uS or so and this is repeated at a 1 KHz rate for a several seconds, paused and restarted.


There appear to be some example designs using various clock generator devices: TI LMK0482 for one.  But our system is simpler since we only have one ADC channel and we are thinking it may just make more sense to output this signal directly from our FPGA and synchronize the signal within.  The same sysref output would have to be fed back into the FPGA to align it with the SYSREF going to the ADC, we think. We are concerned about that implementation. Could someone please point us to some design examples that might be more relevant to our application?


Thanks and Best Regards,

-Tim Starr on behalf of JR@ES