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digital loop back mode of AD9361

Question asked by angleIsDancing on May 11, 2016
Latest reply on Aug 10, 2016 by larsc

Hi all:

     when tuning the digital interface in FPGA, it firstly tunes the receive path. After that switch to digital loop back mode, enable FPGA->device->FPGA prbs, which means that the data flow of the process is FPGA->AD9361's transmit path

->AD9361's receive path->FPGA. In digital loop back mode, how is data transferred from chip's transmit path to chip's receive path?