in the project hdl-hdl_2014_r2, if we send data using DMA, is the IQ correction used in FPGA(receive path)?
The IQ correction is a linear-time-invariant system with a frequency independent response. This means each frequency present in your signal is affected in the same way as if it was the only frequency present in the system and each frequency is affected the same way. So this means the IQ correction works for any kind of signal.
Yes, data flows first through the IQ correction and then to the DMA. For more information please refer to AD9361 HDL Reference Designs [Analog Devices Wiki].
Thank you for your quickly reply. I have seen the webpage I/Q Correction [Analog Devices Wiki] ，there assuming the data is Sinusoidal modulation. if we send other modulation data(for example QPSK data), is the I/Q correction still valid?
If yes, Can you tell me why?
If there is IQ correction in FPGA, is the IQ correction in AD9361 chip needed?
You can use either. I think the IQ correction in the FPGA was primarily added for the AD-FMCOMMS1-EBZ platform which does not have IQ correction in the transceiver.
The I/Q "correction" is used for I/Q rotation in the FMCOMMS5 project.
I/Q Rotation [Analog Devices Wiki]
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