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data flow of digital loop back

Question asked by angleIsDancing on May 9, 2016
Latest reply on May 11, 2016 by angleIsDancing

Hi all:

       In digital interface tuning(in FPGA), when tuning the transmit path, FPGA generates PRBS patterns, then FPGA sends PRBS patterns to AD9361's transmit path by digital interface, lastly FPGA receives PRBS patterns from AD9361's receive path for monitoring. Is the data flow right? if yes, how are the PRBS patterns transferred from AD9361's transmit path to AD9361's receive path? if no, what is the data flow?