HMC704 is a PLL need a extern VCO(VCXO) chip. the datasheet gives the recommond minmum reference frequency is 25MHz with the sinusoidal input or 0.5v/ns skew with square. but actually I want to multiply a 1MHz sine frequency to 100MHz, so is the HMC704 can be used for this function? if not, is there any other chips that can substitude this chip? but phase noise about PLL should be concerned as the vital factor. I have an idea,but I don't know whether it is ok.that is if using a *Schmitt trigger *or comparator to shape 1MHz sine reference into a 1MHz square with skew larger than 0.5v/ns. And I search the comparator chips list ,find that chip DCMP582 meets the requirements.but I don't know how much the chip DCMP582 introduces the phase noise.is it much than 1MHz reference frequency as the PLL HMC704's input directly? if so.this method would lose its meaning. does the low frequency PLL( such as below 1MHz) produce phase noise more than high frequency PLL (such as 100MHz)? if the input reference is not 1MHz ,but 1KHz,what the PLL phase noise would be?

thank you.

Operating the HMC704 with sine reference below the recommended 25MHz was discussed in your other post at https://ez.analog.com/message/250985#comment-250985 .

You will need to convert the 1MHz sine wave to a square wave but the ADCMP582 output driver does not meet the 0.5Vpp minimum input level for the HMC704 reference.

For best performance run the PFD as high as possible since from Eq 1 in the HMC704 datasheet higher PFD rates (f_pd) reduce PLL noise floor. If you convert the 2nd term in the equation into dB form the phase noise floor is:

where FOM=-227 dBc/Hz and f is the output frequency.

Increasing the PFD frequency from 1MHz to 100MHz improve the PLL phase noise floor by 20 dB. Just be careful you must respect the minimum N requirement. In fractional mode N>=20. In integer mode N>=16. For example with Fout=100MHz the maximum PFD frequency is 5Mhz in fractional-N mode.