I'm evaluating the ADF5355 for an application where it is used as fractional-N PLL. In this application, more than one chip is involved. All those chips have to produce the same output frequency with the same phase after the PLL locking. Therefore, the Phase Resync feature has to be ON on each ADF5355 chip.
My point is, how to determine the correct value for the Phase Resync Timer (Register 12) in order to apply the phase resinchronization process just after the locking? In particular, is there anyway to automatically determine the value for the Phase Resync Timer in order to minimize the time to get all the output frequencies in phase?
Moreover, activating the Phase Resync feature on each ADF5355, does it ensure that ALL the ADF5355 output frequencies have the same phase?
Thank you for your support.