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ADSP-21369 S/PDIF Transmitter

Question asked by swapp on Jul 18, 2011
Latest reply on Aug 5, 2011 by jeyanthi.jegadeesan

Hi all!

 

My system, based in ADSP-21369, is clocked by 29.184 MHz.

CCLK frequency is Xin * 24 / 2 = 350.208 MHz.

 

I'm using S/PDIF transmitter to send out internal data for debug purpose.

SPORT / DIT clock signals are generated via PCGC and PCGD.

Since these PCGs cannot be directly routed to SPORT and DIT I'm using external DAI routing for loopback.

 

The following is the code fragment used to program signal routing and clocks timing:

 

 

...


#define CLKIN_Hz                              29184000
#define AUDIO_FS_Hz                       76000
#define AUDIO_BCLK_Hz                   (64 *AUDIO_FS_Hz)
#define AUDIO_MCLK_Hz                   (384 *AUDIO_FS_Hz)


#define PCG_DIV(fin, fout)                   ((int)((fin) / (fout)))
#define PCG_FSPHASE_LO(ph)           (((ph) & 0x3FF) << 20)
#define PCG_FSPHASE_HI(ph)            ((((ph) >> 10) & 0x3FF) << 20)

#define PCG_PW_AC(fin, fout, duty)     (int)((duty) * PCG_DIV(fin, fout))
#define PCG_PW_BD(fin, fout, duty)     (PCG_PW_AC(fin, fout, duty) << 16)


// BCLK routing

SRU(PCG_CLKD_O, DAI_PB03_I);
SRU(HIGH, PBEN03_I);


// LRCK routing
SRU(PCG_FSD_O, DAI_PB04_I);
SRU(HIGH, PBEN04_I);


// MCLK routing
SRU(PCG_CLKC_O, DAI_PB05_I);
SRU(HIGH, PBEN05_I);


// External signal to synchronize PCGD...

SRU(DAI_PB11_O, PCG_SYNC_CLKD_I);
SRU(LOW, PBEN11_I);


// SPORT2 routing
SRU(LOW, SPORT2_DA_I);
SRU(DAI_PB04_O, SPORT2_FS_I);
SRU(DAI_PB03_O, SPORT2_CLK_I);


...

// SPORT2 programming for I2S and DMA transfer

...


// DIT routing
SRU(DAI_PB04_O, DIT_FS_I);
SRU(DAI_PB03_O, DIT_CLK_I);
SRU(DAI_PB05_O, DIT_HFCLK_I);
SRU(SPORT2_DB_O, DIT_DAT_I);

SRU(DIT_O, DAI_PB14_I);
SRU(HIGH, PBEN14_I);


/*

PCGC:
  * CLK = MCLK
      * SOURCE = CLKIN
      * DIV = 1 (bypass - 29.184 MHz)
      * SYNC = 0
  * FS (unused)

*/
*pPCG_CTLC1 = PCG_DIV(CLKIN_Hz, AUDIO_MCLK_Hz);

*pPCG_CTLC0 |= ENCLKC;


/*

PCGD:
  * CLK = BCLK
      * SOURCE = CLKIN
      * DIV = 6 (4.864 MHz)
      * SYNC = 1
  * FS = LRCK
      * SOURCE = CLKIN
      * DIV = 384 (76 KHz)
      * PHASE = 3 (to guarantee edge alignment to falling edge of PCG_CLKD).
      * PW = 192
      * SYNC = 1

*/   
*pPCG_CTLD0 = PCG_FSPHASE_HI(3) + PCG_DIV(CLKIN_Hz, AUDIO_FS_Hz);
*pPCG_CTLD1 = PCG_FSPHASE_LO(3) + PCG_DIV(CLKIN_Hz, AUDIO_BCLK_Hz);
*pPCG_PW2 = PCG_PW_BD(CLKIN_Hz, AUDIO_FS_Hz, 0.5);
*pPCG_SYNC2 = CLKD_SYNC | FSD_SYNC;

*pPCG_CTLD0 |= ENCLKD | ENFSD;

 

// DIT programming

*pDITCTL =    DIT_EN |
                      DIT_FREQ384 |
                      DIT_IN_I2S |
                      DIT_AUTO;

...

 

 

 

Observing the following signals

* BCLK (DAI3)

* LRCK (DAI4)

* MCLK (DAI5)

* DIT_O (DAI14)

I see correct clocks timing but heavy jitter on DIT_O signal while expecting DIT_O transitions locked to MCLK edges.

 

Any suggestion?

Thanks,

Andrea

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