AnsweredAssumed Answered


Question asked by thw on May 6, 2016
Latest reply on May 6, 2016 by MClifford

Dear Sirs,


I'm interfaceing an AD7760 to an FPGA and I experienced that, during setting a configuration register resp. reading status registers, the ADC is signaling ADC-results by pulling DRDY low. Is there no arbitration? In the output stream Status-Register an ADC-values are intermixed. The datasheet of the AD7760 is lacking of detailed information there.


Thanks in advance