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AD9640 output test mode.

Question asked by williamchen on Jul 18, 2011
Latest reply on Jul 21, 2011 by williamchen

Dear all,

 

Please help me.

 

First, I use DRVDD = 1.8V, differential clock input, and the output test mode is OK.

Then I swith to use DRVDD = 3.3V, single end clock input.

The SPI read is OK, and I can read out Chip ID (address 0x01)

But when I try output test mode, outputs are all high.

 

I'm wondering if the clock is not accept by AD9640, so please check the clock waveform for me.

 

Datasheet reference design:

 

AD9640_CLOCK.jpg

 

Our design:

CLK.jpg

 

The waveform of point A is:

 

ad2.jpg

 

And the waveform of point B is:

 

 

ad1.jpg

 

At point B,

(1) Low level is 480mV, high level is 1.88V.

(2) Vpp is 2.02V

(3) Duty cycle is 49.59%

(4) Vrms is 1.407V

 

     Datasheet:

AD9640.jpg

 

Is the clock not good or there may be other mistakes?

Please give me a direction to debug.

Thank you!

 

Best Wishes,

William

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