I am using the SC584 Sharc DSP
Using the regular core fir() function seems to not be using the feature above (PEy registers)
Where can I find an example code or any explanation regarding this issue?
All the source codes are available in the CCES Installation path
“.\Analog Devices\CrossCore Embedded Studio 2.2.0\SHARC\lib\src\libdsp_src”
The library codes present here have a SIMD version for fir_decima, fir_interp, fir_vec , all optimized for SHARC+ Core architecture but the fir() function has a SISD implementation.
You can refer to the application note EE375 “Migrating Legacy SHARC to ADSP-SC58x/2158x SHARC+ Processors” to get the SIMD implementation of FIR function optimized for SHARC+ Core architecture
Thanks for the information.
What is the need to go into code migration from Sharc to Sharc+ if the fir() function I have, works on Sharc+ ?
Is it such a big problem to do the changes from SISD to SIMD for the specific function/loop ?
SHARC codes are compatible with SHARC+ core, but the difference is the performance. In some cases , you may see the same code giving better performance in SHARC+ core and in some other cases, the performance may have degraded in SHARC+ . For the cases where the performance is degraded, we can to optimize the code to suit the new SHARC+ architecture and still get the same performance as that in SHARC core.
There is no extra effort required in moving from SISD to SIMD implementation due to architectural change in SHARC+ core. It is same as it was in earlier SHARC core.
Specific to fir() library function, I see that the “CCES Library manuals for the SHARC processor” (http://www.analog.com/media/en/dsp-documentation/software-manuals/cces2-2-0_SharcLibrary_mn_rev1-5.pdf) says that the vector version of the fir() uses SIMD mode. (Pg 3.232). Is this the function that you are using ?
No, we need the non vector fir() function which is the single sample fir()
I tried to use the FIR accelerator , but it is irrelevant for single sample fir()
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