I have an encountered an issue with the AD9361 baseband PLL driver initialization when the driver is configured to use a 50 MHz reference clock. Specifically, if an initialization is run with BB_REFCLK set to 50 MHz and BBPLL_CLK set to 800 MHz, the conditional statement on line 130 of util.c evaluates to FALSE and the function ad9361_bbpll_set_rate() is never called. To temporarily work around this, I have modified ad9361.c to force phy->clks[BBPLL_CLK]->rate to zero just before the call to clk_set_rate() on line 4189.
It happens anytime the initial BBPLL is 16 times higher than the reference clock (not only in the 800 - 50 case).
ad9361_bbpll_set_rate() is not called because it wouldn't do anything else than setting those registers to same values they are already set.
However, this issue with this is that the BBPLL simply remains uninitialized upon system startup. It might be possible to set BBPLL_CLK to a different frequency and call ad9361_set_trx_clock_chain(), then reset it to800 MHz and repeat, but my application cannot afford that additional startup time. I want the BBPLL to initialize the first time I call ad9361_set_trx_clock_chain().
Am I missing an API call to force ad9361_set_trx_clock_chain() to properly initialize the BPLL when BBPLL desired frequency is 16 times greater than the reference? Thanks!