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21488 ASRC noob help

Question asked by jbagg on May 4, 2016
Latest reply on May 10, 2016 by Jithul_Janardhanan

I'm new to Sharc DSPs and specifically the 21488 hardware sample rate converter modules.  The audio output of the SRC is noisy.  When I mute the input source, I have hiss instead of silence.  Looking on a scope, with the input muted, I see the 2-3 LSBs jumping around.  Attached is my c code that sets everything up.  I'm running this using CCES 2.1 using an ICE1000.


---[ Output clock setup ]---

The sharc 21488 has a 24.576MHz (instead of 25Mhz) oscillator.  I'm using the PCG to generate the output clocks

Master clock = 6.144Mhz (PCG B div 4)

Bit clock = 3.072Mhz (PCG A div 8)

FS clock = 48Khz (PCG FSA div 512)


---[ SRC setup ]---

// inputs

SRU(DAI_PB07_O, SRC0_CLK_IP_I);     // 2.82Mhz input bit clock

SRU(DAI_PB08_O, SRC0_FS_IP_I);          // 44.1Khz input FS clock

SRU(DAI_PB05_O, SRC0_DAT_IP_I);        // = I2S data input

// SRC0_TDM_IP_O goes no where?


// outputs

SRU(PCG_CLKA_O, SRC0_CLK_OP_I);     // 3.072Mhz output bit clock

SRU(PCG_FSA_O, SRC0_FS_OP_I);          // 48Khz output FS clock


SRU(SRC0_DAT_OP_O, DAI_PB12_I);        // = I2S data output

SRU(LOW, SRC0_TDM_OP_I);                    // = 0v for master phase matched mode


*pSRCCTL0 = SRC0_SMODEIN0 | SRC0_SMODEOUT0 | SRC0_ENABLE;     // I2S input 24-bit, I2S output 24-bit


Also, If I turn on matched phase mode, I never see the meta data in the lower 8 bits (bits 25-32), they are always zero.