If I am using a DDS for clocking applications. What is the type of reconstruction filter used in DDS, is it supposed to be a analog filter or can we manage with digital filter ?
In our evaluation boards, we often use an analog filter. A 7th order elliptic filter.
Is the Analog filter part of the Chip or needs to be discrete components outside the chip.
Depending on your application but in our boards, they were implemented using discrete components.
In number of the DDS chips from analog devices, there is a block as clock multiplier. Can you please let me know what kind of multiplier is being implemented. Is it hybrid with DDS and PLL ?
Where you see a clock multiplier reference, we are referring to a PLL based clock multiplier.
Is there a way to multiply frequency (in order of 8X or more) using DDS solution or other solutions.
DDS technology inherently does division. to multiply up a frequency, you either need to work with images in higher Nyquist zones, or utilize a PLL. Some of our DDS chips have PLL based multipliers designed into them; these could also be used.
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