I am using the project hdl-hdl_2014_r2, the "re-customize ip " block of axi_ad9361_adc_dma is below.
Could anybody tell me where I can find the description of each entry in the picture?
An extensive description of these parameters is currently not available. But if you update your design to the ADI HDL release you get a more human readable version of the dialog:
Moved to FPGA Reference Designs community.
Could you tell me what does the entry "DMA Transfer Length Register Width" represent for? why is it set to 24?
In this case, the maximum length of one transfer is 2^24 (16777216) bytes. If more data has to be transferred, multiple transfers have to be configured.
What is the maximum number of "Maximum Bytes per Burst" ? I tried 256, but it refuses to work. Thanks!
For AXI3 it's 16 beats per burst and 1 beat transfers the bus-width worth of data. So with 64 bit buswidth the maximum bytes per burst is 128 for AXI3.
On the Zynq the HP interconnects are AXI3 only so switching to AXI4 will not allow any improvements.
I tried to send fixed length bursts of 352 bytes to the ARM through DMA randomly. The ARM sometimes gets wrong order of data in a burst. Most bursts arrive the ARM correctly. I suspect the DMA 128 bytes number is too small and the ARM reading is getting overfolowed. What could be the problem?
Thanks a lot!
The burst size should not be a problem. Consecutive bursts are guaranteed to arrive in the order they where issued. Is it possible that the data gets swapped before it reaches the DMA?
I am sure data is reaching to DMA coreectly. When use the DMA, we make fifo_wr_sync=fifo_wr_en=dvalid, and feed 64 bits data to fifo_wr_din. Is this setting correct?
Sorry for the delayed response. Yes, that sounds correct. If you assert the sync signal for each sample you can also just completely disable the transfer start synchronization support.
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