I am using the fmcjesdadc1-ebz with a ZC706 and the HDL reference design with bare-metal code. When I look at the ADC data on the ILA core in Vivado's Hardware Manager, Channels 0 and 1 look like correct, but Channels 2 and 3 appear to be hitting the positive & negative limits (+/- 8191). When I ground all of the inputs (or leave them floating), Channels 1 & 2 have a slight positive offset of about 20, but Channels 2 & 3 are around -8170. The attached image displays this behavior. In this image, the same sine wave signal is being input into Channels 0 & 2, while Channels 1 & 3 are left floating (they would look the same if they were grounded).
I also tried using the SD card image provided by Analog Devices. When I use this image, all four channels have a small positive offset (between 5 and 35) with the inputs grounded, and I can see the correct signal when I apply an input. I verified the ADC values in the oscilloscope software in Linux that came with the SD card image, and I also verified the ADC values with the ILA core in Vivado's Hardware Manager.
This leads me to believe that the hardware is working properly, but I am not configuring the 2nd ADC (channels 2 & 3) correctly in my bare-metal code. However, as far as I can tell, both ADCs have been configured the same way.
Are there any register settings, or anything else that would cause this behavior on one of the ADCs?
Thank you in advance