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SPDIF/SRC freezes on DC offset

Question asked by PhilipJ on May 2, 2016
Latest reply on Jun 7, 2016 by DaveThib

I have a problem using the SPDIF input through SRC.

When the SPDIF source is removed one or other freezes on a random DC offset value. In my design this is passed through to the output which is driving a DAC resulting in an unwanted DC voltage offset at the DAC's output buffer.

I have proved this by putting a Mute in series with the SPDIF signal and when muted the digital output stream to the DAC reverts to zero.

Any suggestions for auto muting based on the SPDIF or SRC lock bit?

I don't want to use the embedded signal level in the SPDIF because this unwanted DC offset will probably mess it up.

 

regards

PhilipJ

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