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ADDI7013 - HD/VD, CLPOB and SYNC_DELAY

Question asked by christiansier on Apr 29, 2016
Latest reply on May 5, 2016 by TFAnalog

Greetings all,

 

We use the new ADDI7013 Dual-Channel CCD Signal Processor to read a CCD linear image sensor. The sensor outputs only one line with 2048 pixels, divided into eight segments of 4 dummy pixels and 256 valid pixels (therefore we use the ADDI7013 four times). After being processed by the ADDI7013, the pixel data is sent to a FPGA that runs the remaining processing. The FPGA is configured as the master ip, so the ADDI7013 is set into slave mode and will receive most side signals (like HD and VD) from the FPGA.

 

As the chip is very new, we have encountered some problems with the data sheet.

 

First thing is about HD and VD. The timing specifications note that VD pulse width has to be at least one HD period which sounds reasonable (one frame has a minimum of one line).  Thus we control the vertical and horizontal sync signal identical. But figure 8 and 9 are confusing us because our experience with image sensors conflicts with the shown figures. Horizontal sync (we would also call this line valid) should never be set without vertical sync (we call this frame valid) being set. Is there something wrong with our understanding of HD and VD when accessing the ADDI7013 in slave mode?

 

Next we are unsure about the optical black clamp. Our understanding is we can use the clamp circuit to balance temperature drift. Is this correct? If yes, how is the optical black clamping controlled? The datasheet mentions that the clamping should be done for every horizontal line. How can we control the start and end of the optical black clamping (will it start at a fixed time stamp like falling edge of HD or can we set it freely)? We only have four dummy pixels before the valid pixel data is received, is this enough? The datasheet mentions that the clamping duration has to be at least 20 pixels. Is it also possible to forego the clamping during our first field tests?

 

Finally there is an option called SYNC_DELAY in register 0xc09a. The two descriptions do not sound like they would go together so we do not understand the meaning of this option. Our assumption is we can delay the start of the pixel data after the sync words are transmitted so SYNC_DELAY should be seen in figure 53. We can definitely say that we don’t get correct data if we don’t set the value.

 

Regards
Christian Sier

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