I am using the AD5293 with the zipper reduction circuit (data sheet and app-note 1209). Am I correct in saying that the SYNC output goes high at zero crossing to transfer data to the selected register.
When the signal crosses the window, the logic of the /SYNC pin of the AD5293 will depend on the /SYNC input of the user. In other words, if the user /SYNC is low, then data transfer will not happen. If user /SYNC is high, and a valid 16-bit data has been clocked in, then the DAC will perform the indicated command.
I labeled the diagram below to show what would be the values of the logic gates.
If you have any further questions, please do not hesitate to ask.
Thank you Mark,
Another question: Is there a limit to the time between when the /SYNC goes low to the time that the DATA is CLK'd? I want to manually take the /SYNC low, wait a period of time then clock the data, then wait a period of time and then take the /SYNC high to transfer the serial register to the RDAC. I know the /SYNC must remain low during the clocking of data and then taken high. Thank you for you help.
I don't think there is a limit on how low the /SYNC can go low. My guess is that it's alright to wait a period of time before pulling the /SYNC high. Although it is worth taking note that you need a minimum of 1 ns from the SCLK falling edge to the /SYNC rising edge (t7) as indicated in the timing diagram below.
Very helpful thank you!
Update: description added to image:
It worked great, maximum delay is ~ 8ms / this is the time out if no zero crossing is detected.
Thank you for your help.
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