Hi, I want to use the DDS to generate a sine wave (around 500Hz, 0.25Vpk) with very low noise (less then 0.5 uV/Hz). Is there any DDS or other parts could meet this requirement? Thanks!
Hi, all ADI DDS products can run as low as 0Hz, so 500Hz is no problem. The frequency resolution
across the DDS portifoliio ranges from 24 bits to 48 bits. The AD9912 DDS has the best phase noise and SFDR performance of all the DDSs released so far (7/15/11). Less the AD9912, I would recommend looking at the AD9910, AD9911 or AD9859.
Note, the customer evaluation boards for the all the DDSs above have a transformer coupling the DAC output (DDS output), so 500Hz output would be an issue for the transformer's low end bandwidth specification.
Hope this helps.
Because a DDS relies on a DAC to convert a digital sinusoid to a real world signal, harmonics will appear in the output spectrum. The harmonics are a consequence of the fact that no DAC is perfect. In terms of signal level, DAC harmonics constitute the highest level of unwanted signals in the output spectrum. That said, you will need a narrowband filter centered at 500Hz to suppress the DAC harmonics as much as possible.
As an example, assume a 2nd harmonic (appearing at 1kHz given a 500Hz fundamental) with a magnitude of -60dBc (1/1000). If the fundamental signal has a magnitude of 250mV rms, then the harmonic has a magnitude of 250uV rms, which is 500 times higher than the 0.5uV/Hz requirement. This implies that you would need a filter that provides at least 54dB of rejection 500Hz away from the fundamental (a fairly demanding filter). Of course, a DAC that yields harmonics less than -60dBc would result in a less stringent filtering requirement.
Aside from providing adequate filtering, you would want to use the highest possible sampling clock frequency for the DDS. This will help spread out the quantization noise associated with the DAC.
In the simplest sense, a DDS is a fancy frequency divider. It takes the sampling clock frequency and divides it down to the desired output frequency per the applied digital frequency tuning word. Because a DDS is essentially a frequency divider, noise on the sampling clock also appears at the output. Hence, you will want to use a sampling clock that meets the 0.5uV/Hz noise requirement.
The next consideration is phase truncation spurs. The short answer on this is to use a DDS that has a DAC with as many bits as possible. For example, assuming a properly designed DDS, a 14-bit DAC is a better choice than a 10-bit DAC in terms of phase truncation spurs. A DDS with a 14-bit DAC sampling at 100MHz and generating a 500Hz output signal should yield truncation spurs no greater than about -115dBc. For a 250mV rms fundamental, the worst phase truncation spur would be approximately 0.44uV rms.
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