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How to keep fixed phase relation HMC7044

Question asked by Joho Employee on Apr 27, 2016
Latest reply on Apr 29, 2016 by kpeker

We have an application where we intend to use HMC7044 for clocking two AD9680 at 496 MHz from a common external reference signal at 62 MHz (applied at CLKIN0). The sampling clock is generated by dividing by 6 the internal VCO (PLL2) from 2976 MHz. We understand that HMC7044 can generate phase aligned clock among outputs but it's not clear to us (if even possible) how to keep fixed (system restart invariant) phase relation between applied CLKIN0 signal at 62 MHz and the 496 MHz outputs. Because of the division by 6 of 2976 MHz we expect to have 6 different phase relations between CLKIN0 and CLKoutX edges: 0, 336 ps, 672 ps, 1008 ps, 1344 ps and 1680 ps. How can we use HMC7044 to automatically compensate these phase uncertainty.                

Other PLL parameters are:
R1 =  2
N1 =  4
R2 =  2
N2 =  48

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