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I and Q getting swapped in received signal on Rx1 on AD9361

Question asked by abmartin on Apr 27, 2016
Latest reply on Apr 27, 2016 by larsc


  I am running a Linux application using the AD9361 (on Zync706). The use case is Described below.

Hardware Setup -

- AD9361 SDR Chip AD-FMCOMMS2-EBZ on zc706 zync board.

- I am using a modified version of the ad9361-iiostream C application to configure as below:

     + FDD Mode.

     + TX1 and TX2 enabled. Tx Sampling Frequency - 20MHz; RF Bandwidth - 56MHz

     + RX1 and RX2 enabled. Rx Sampling Frequency - 20MHz; RF Bandwidth - 56MHz

     + TX LO - 2.4GHz; RX LO - 2.4GHz

     + AGC Mode - Manual Hardware Gain-69

     + Tx Buffer is configured as non cyclic.


Tx1 and Rx1 ports and connected via cable with fixed attenuation.

Then I transmit a signal on Tx1 (I and Q) and receive on Rx1 (I and Q) Which I am plotting as a waveform.



What I am observing is that When I run the above usecase repeatedly, sometimes the I and Q signal of the Rx is getting inter changed from that of the transmitted signal. I have attached the observed waveforms.

There are runs where the I and Q are proper, but the swapping happens often.


What we suspect is below:

At the ADI IPCore side, which samples the TX and RX data, there are two data valid signals for TX and RX.

When we observe the signals using Internal Logic Analyser, we see that the two signals are either in sync, or shifted by 1, 2, 3 clock cycles. Due to this out of sync signals, the wrong sampling of the data might causing the I and Q data to be swapped. And could also explain why there are four types of swapped waveforms observed.


Could anyone provide any suggestions on our observation and any possible solution to remove the swapping.