Dear support,

I adopt the ADF4351 in my design as local oscillator (LO), in particular the LO operates in 4212.5MHz to 4312.5MHz bandwidth with 33 equally spaced channels with 3.125MHz fixed separation. The input reference is a 100MHz signal.

In this configuration, the ADF4351 works as Integer-N PLL and I adopt the following values for the RF dividers:

R = 32 (fixed), or 16 (fixed) enabling ÷2 divider;

D = 0;

T = 0;

FRAC = 0;

MOD = 2;

DIV = 1;

INT spans between 1348 to 1380;

My concerning is about the ADF4351 output phase noise in this configuration where the INT values has a quite high absolute value and it spans over a wide range of values.

Does the value of INT and R divider could influence the phase noise performance in any way?

Simulating with ADIsimPLL the ADF4351 output it seams no degradation in the SSB spectrum for every value of INT, is it correct?

Thank you for your reply

The ADIsimPLL simulation is correct.

In all PLLs, when you double the PFD frequency, and halve the N value, the in-band (Chip) phase noise improves by 3 dB. The PLL phase noise equation is:

Normalized phase noise floor = Measured in-band phase noise - 10 log Fpfd - 20 log N.Because the impact of the N divider is scaled twice the impact of the PFD frequency, we get the 3 dB result.

Yes - fractional-N mode does have more spurs. However, you can use lower spur mode on the ADF4351 to mitigate a lot of these fractional spurs. Depending on your frequency plan, you may be able to avoid the integer boundary spurs by avoiding output frequencies near integer boundaries.