I am going to use the AD9136 DAC that have interface JESD204B. I assume DAC sampling rate (fs) is 1.2288 GHz and JESD204B lane rate is 6.144 GHz
I have read the datasheet and I have some question.
The Board have clock generator (AD9520-1), I will not use DAC PLL (in AD9136). I checked my clock below block diagram.
Red line may be 1.2288 GHz.
“SERDES PLL” input named DACCLK, so SERDES PLL input clock is 1.2288 GHz as device clock.
In figure 46, fref is (BIT RATE / 40). Because I using lane rate 6.144 GHz, fref is 153.6 MHz. But I wonder where that comes fref (153.6 MHz). I’m confused with the relation of DACCLK and fref.
Can you explain this?
Because AD9136 datasheet NO have output stage configuration. (Only I get guide by EVM schematics.) I struggle.
I will use AD9680 ADC with AD9136. AD9680 recommended to balun parts BAL-0006SM. I want to reduce part, so I wish BAL-0006SM use to AD9136’s balun.
Can you recommend AD9136, balun configuration using BAL-0006SM?