I am currently trying to interface an AD9913 with an Altera FPGA using the 3-wire SPI interface. The ADC in question has a ref_clk that is a 25MHz crystal. I am using a SCLK of 50KHz. I have verified that the timing requirements have been met for SDA, SCL, and SC, yet after sending a read request to any address the chip simply fails to 'take control' of the SDA line and send any data back. Does anything such as the ref_clk need to be configured before register states can be read out? I have verified that IO_UPDATE, PWR_DWN_CLT, and MASTER_RESET are all pulled down. After working with an intermittent and buggy eval board and this unresponsive chip I am sadly beginning to question this line of products.