In our our custom design we are using ADCLK846 Clock buffer for clocking to HD-SDI block
We need LVDS clock input and LVDS output clock. I am confuse by Table 8 mention in data sheet for interface options for each type of connection.
Supply (V) Logic Common Mode (V)
1.5 HSTL 0.75
Means if we require LVDS logic,supply voltage should be 1.5 V but in data sheet at the top it is mentioned that it is 1.8 V, 6 LVDS/12 CMOS Outputs Low Power Clock Fanout Buffer.
I require only LVDS input and LVDS output logic please clear what supply should i give to the IC whether it is 1.5 V or 1.8 V