I am considering using this device in a measurement instrument which relies upon very low phase drift between two clocks. The AD9578 has two outputs driven from each PLL. With this arrangement one would expect any low frequency drift or jitter from the PLL to be common mode between the two outputs, even when the dividers are set to different values. However the data sheet specifies an offset skew between the two outputs. What is the origin of this? What is the expected temperature variation and long term stability of this skew? ( I will be using LVPECL mode).
This skew is stated to be independent of the divide value. Does this mean the output dividers are fully synchronous?
Why is the skew specified for positive going outputs ( with a differential output this does not make sense)?
I would like to wire OR two of the outputs , say output2 and output3, both set to LVPECL, so I can switch between two frequencies using the enable bits. The data sheet states that unused outputs are high impedance. Can you confirm that the wired OR arrangement will work?