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DAQ2&KCU105 FPGA Reference Design c0_ddr4_dm_dbi_n constraint problem

Question asked by -2dbc on Apr 25, 2016
Latest reply on May 6, 2016 by rejeesh

Hi All,


I can get data from DAQ2 by using your FPGA Reference Design. ILA probes display to me that your no-os drivers works fine and ADC_CLOCK is ok.

I want to merge your ref. design with mine. I added my top module to your ref. design and bit stream generation failed.

I think there is a confusion between "ddr4_dm_n" and "ddr4_dm_dbi_n".


There are errors like these:

1. [Mig 66-99] Memory Core Error - [system_top_ins/i_system_wrapper/system_i/axi_ddr_cntrl] MIG Instance port(s) c0_ddr4_dm_dbi_n[0],c0_ddr4_dm_dbi_n[2],c0_ddr4_dm_dbi_n[3],c0_ddr4_dm_dbi_n[4],c0_ddr4_dm_dbi_n[5],c0_ddr4_dm_dbi_n[6],c0_ddr4_dm_dbi_n[7],c0_ddr4_dm_dbi_n[1] is/are not connected to top level instance of the design


2.kcu105_system_constr.xdc includes pin assignments like these:

set_property -dict  {PACKAGE_PIN  AD21} [get_ports ddr4_dm_n[0]]

set_property -dict  {PACKAGE_PIN  AE25} [get_ports ddr4_dm_n[1]]

set_property -dict  {PACKAGE_PIN  AJ21} [get_ports ddr4_dm_n[2]]

set_property -dict  {PACKAGE_PIN  AM21} [get_ports ddr4_dm_n[3]]

set_property -dict  {PACKAGE_PIN  AH26} [get_ports ddr4_dm_n[4]]

set_property -dict  {PACKAGE_PIN  AN26} [get_ports ddr4_dm_n[5]]

set_property -dict  {PACKAGE_PIN  AJ29} [get_ports ddr4_dm_n[6]]

set_property -dict  {PACKAGE_PIN  AL32} [get_ports ddr4_dm_n[7]]


3. system_axi_ddr_cntrl_0.xdc includes pin assignments like these:

set_property OUTPUT_IMPEDANCE RDRV_40_40 [ get_ports "c0_ddr4_dm_dbi_n[3]" ]

set_property OUTPUT_IMPEDANCE RDRV_40_40 [ get_ports "c0_ddr4_dm_dbi_n[4]" ]....


4. axi_ddr_cntrl has a pin that named as "c0_ddr4_dm_dbi_n" in your Block design.

(Screenshot is attached.)


5. system.v file includes line like this:

system_axi_ddr_cntrl_0 axi_ddr_cntrl






This line has naming conversion from c0_ddr4_dm_dbi_n to c0_ddr4_dm_n.


How can I solve this problem?


Thanks in advance.