AD9914 sync_clk trouble

Discussion created by e.charre@synopsisgroup.com on Apr 25, 2016
Latest reply on Apr 26, 2016 by e.charre@synopsisgroup.com

Hi every one.

We are using AD9914 with direct ref. clock at 3.0GHz. Most of the time it is working well, but....

We discover a trouble about sync_clk output, the phase of this signal change time to time.

I also capture another effect, most of time, this signal is referred from GND with 33% ratio, but sometime, this signal become and stay inverted, referred from 3.3v !! See attached picture.

The rising/falling time of "sync_clk" is partially limited by my oscilloscope, but i am convinced it is also limited by AD9914 itself.

In any case, is someone understand why "sync_clk" change its phase ?

Why "sync_clk" become inverted and referred to +3.3V ?


I have to say our schematic about ref. clock design is exactly the same as AD9914 evaluation board !


Thank's for help.