On page 97 of the datasheet it is written that the "slave accepts data from an external master up to 5.12 Mbps." This appears to conflict with the minimum value of the data input hold time t_{DHD}, on page 13, table 5, which is specified as 2 x t_{UCLK}. Given that t_{SL} must be at least t_{DHD} (minus the duration – which can be negative – SPI masters keep the data valid on the MOSI line after the output changing SCLK edge), the clock period may not be shorter than

2 x t_{DHD }= 2 x 2 x t_{UCLK} ≈ 391ns which results in a max. bitrate of 2.56 Mbps. This is only half of the value given on page 97.

If I am not doing something wrong in my calculation, which of these max. frequency values is the correct one?

The ADuC7061 (at least the piece that I'm testing), by the way, appears to accept data even at 7.5MHz, which suggests a smaller minimum t_{DHD} value.

Thanks for high-lighting that conflict - on short 5.12 Mbps have been tested to work.

We will check the details and update this in a future revision of the data-sheet.