I hope this is an easy one.
One of our software team discovered that he could not reliably receive data over the SPI bus when he loaded up a FIFO available to the host processor side of the SPI interface and just let the interface rip. I pointed out to him that the IMU requires a delay between each word, and, unfortunately, this particular interface does not have the capability for the user to set a "stall" time when using the FIFO. He had already re-written his routine to send one word at a time and he is now going to change the routine such that it enforces the stall time.
He does have questions regarding the Register Specific Stall times spelled out in Table 3 of the Rev C data sheet. Specifically the first 4 registers in that table (FNCTIO_CTRL, FLTR_BNK0, FLTR_BNK1, NULL_CFG).
1. Do the stall times in the table only apply during writes to the registers, such that we can use a 2us stall during reads?
2. Does the time specified apply to every byte during a write, or only the most significant byte (i.e. after the register is actually written)?