For Starting to evaluate the AD9136-EBZ,
Quick Start Guide or manual about "SPIPro" is available ?
I can not understand how to set the top panel.
For example, what is "Fin" at "Quick Configure" ?
The following website shows the various Quick Start Guides for the different AD9136 evaluation boards that you can use as reference. We also have a newer software called "ACE" (Analysis | Control | Evaluation) that we also have support for the AD9136-EBZ you can try to use which has a bit more features than the SPI PRO. You can download this software from the ACE Wiki site (Analysis | Control | Evaluation (ACE) Software [Analog Devices Wiki]).
Regarding "Fin", the wizard (for both SPI PRO and ACE) assumes if you are not using the DAC PLL that you are sending a clock to the AD9516 clock chip (J1 SMA connector) that is equal to the DAC rate you wish to use and you do not need to input an "Fin" value (why it is grayed out). If instead you are using the PLL, then "Fin" is the clock that is sent to J1 (not necessarily the DAC clock, could be the DAC PLL reference clock frequency or may need to be higher based on the mode and FPGA clock rate needed). "RefClk" is the clock frequency you wish the AD9516 clock chip to generate from the "Fin" clock to send to the DAC for it's PLL reference clock frequency.
For your mentioned condition, the FPGA will need a clock of 491.52MHz, therefore you will need to supply at least that frequency to the board so the AD9516 can divide the clock down for the DAC PLL Reference Clock and FPGA clock. In that case use 491.52MHz for "Fin". The DPG3 requires it's FPGA clock to be the LaneRate/20 whereas the ADS7 (if using the FMC evaluation board) requires LaneRate/40 for it's FPGA clock so you can calculate the minimum frequency needed for "Fin" in depending on your JESD Mode Parameters (LaneRate = (20*FDAC*M)/(L*Interpolation)).
Additional question about AD9136 SPIPro.
Using the DAC PLL "on" , what is the relation between "refCLK", Fin" and "FDAC" ?
"DPG clock error" is indications, pop up.
To configure following setting at "Quick Configure" ,
how to caluclate the "Fin" ?
Links = single link
JESD Mode = 11
subclass = 1
Interpolation = 1
DAC PLL = ON
FDAC = 1.96608GHz
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