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AD9106 stable at multiples of 3MHz Clock

Question asked by TheShadders on Apr 21, 2016
Latest reply on Sep 13, 2017 by TheShadders



I am using the AD9106 to output two in-phase sine waves on output 1 and 2. I am using the same commands as I posted here: AD9106 Discontinuities


I have noticed that the outputs are only in-phase when my clock has a frequency that is a multiple of 3MHz. This is incredibly strange. When the clock is not a multiple of 3MHz, the phases of outputs 1 and 2 drift relative to each other. If I power off, change frequency to 3, 6, 9 MHz, etc, power on my board, and resend those commands, the outputs remain in phase. Also, the drift is worse for certain frequencies.


Additionally, it appears that the phase accumulator is stepping through the sine lookup table when it should not be--the output changes at random times of the clock cycle, and not on the high/low transitions. At multiples of 3MHz, the DAC outputs transition as expected--on the rising clock.


Have tried using a function generator and LVDS driver to stimulate the clock. I cannot change the frequency of my LVDS (120MHz), but all measurements point to the clock stimulus being within the datasheet specs, and this drift is there. With the function generator the relative phase drive At first I thought I wan't sending the correct SPI commands, but after using the function generator to stimulate, and getting the correct behavior, albeit only at certain frequencies, I think I have the SPI commands figured out, and it must have something to do with the clock.